Abstract:Trace Caching, Current Processors requires high band width instruction supply. Trace caching is an emerging solution to meet the above requirement.
It is possible that trace construction can be enhanced with optimization functionalities that can increase performance and reduce power. Performance increases and power decreases may be attained if selected traces are optimized to traces with more parallelism and/or having fewer instructions. Some of the important dimensions of the design space explored in this work are: front-end microarchitecture, criteria for long trace selection, value based optimizations, performance and power optimizations and power estimation.